Verify hardware design IP functionality from test plan to RTL signoff

Design and implement the next-generation PCIe verification architecture using SystemVerilog

Create test plans and execute portions or all of test plans for the design IP

5+ years experience with design verification using SystemVerilog and SystemC, using Perl or Python

Develop and manage simulation regression environment for design IP

For immediate confidential consideration, please apply online today!

Education Requirements: BS/MS EE

To apply: Apply online at: http://app.cvtracer.com/public/726389002/apply/applyonline.jsp?Joid=39774&Jo=Sr.++Design+Verification+Engineer